1. Field of the Invention
The present invention relates generally to systems on chips, and in particular to methods and mechanisms for routing transactions in a system on chip.
2. Description of the Related Art
Systems on chips (SoCs) are increasing in complexity and size due to continual technological advances in the electronics industry. A common SoC may include multiple input/output (I/O) devices connected to a processor complex containing one or more processors. The processor complex may typically include one or more processors and one or more caches, and the processor complex may be coupled to a CPU port of a memory controller through which the processor complex may access a memory. The I/O devices may be coupled to a coherency port on the processor complex and access memory through the CPU port of the memory controller.
A portion of the traffic from the I/O devices may be cache coherent. Another portion of the traffic from the I/O devices may be low-performance transactions, and some of the low-performance transactions may be directed to non-shareable memory. Typically, the cost of checking every transaction for cache coherency is high, in terms of hardware, performance, and power. In addition, the traffic from the I/O devices may compete with the processor complex for memory bandwidth on the CPU port on the memory controller. Furthermore, the traffic from the I/O devices may also unnecessarily cause snoop activity to take place in the processor complex.